The present invention relates to the production of semi-conductor integrated circuits, particularly circuits including windows exposing contact pads and fused elements that can be selectively blown to achieve different circuit functions and capabilities.
It is known to incorporate fuse elements into semi-conductor integrated circuits to enable permanent alteration of a basic circuit design, i.e., to produce the so-called application specific integrated circuits (ASIC's). See, e.g., Takayama et al. U.S. Pat. No. 4,536,949. When left undisturbed, the fuse elements provide conductor paths between certain circuit devices. The fuses may also serve as resistive elements. The fuses can be blown to destroy selected paths of conductivity, whereby a circuit function can be permanently altered, i.e. customized. Typically, the fuse elements are burned off (blown) by impinging on the fuse a high energy laser beam, or by application of an electrical current to the fuse element. A high degree of production efficiency is achieved with fused integrated circuits since a range of functions and capabilities can be achieved with a single basic circuit design. Moreover, defective redundant cells, e.g., in a DRAM chip, can be isolated using selectively placed fuse elements.
When a fuse element is embedded underneath an insulative chip layer, it is necessary to provide a window above the fuse element in order to allow for the escape of hot gases when the fuse is blown. Otherwise, the hot gases and pressures generated thereby could cause thermal and mechanical damage to the surrounding chip structure. Additionally, when a laser is used to blow the fuse, a window is necessary to allow the laser beam to impinge on the fuse element.
Recently it has been recognized that it is desirable to form the window above the fuse element such that a thin layer of insulative material remains over the fuse element. The thin layer protects the fuse element from corrosion, and also improves the efficiency of the fuse blow through the generation and retention of additional heat therein. Referring to FIG. 3, the conventional technique for forming such a window has been to place the fuse elements 1 (only one shown) on a chip layer 3 positioned below a primary conducting path including one or more contact pads 5. By placing the fuse element 1 at a position below contact pad 5, a window 7 can be formed above the fuse element 1 in the same etching step used to form a window 9 above contact pad 5. Apertures formed by a resist pattern 10 are used to form windows 7 and 9 during the etching step. These apertures (which correspond in size to the windows formed thereby) have widths just slightly smaller than the respective fuse element and contact pads. For example, the fuse windows may have a width of 10 .mu.m. The contact pad windows 9 may have a width of 80 .mu.m. Due to the relatively small window size differential, the etch rate at each window does not differ significantly. Since the insulative layer 11 is etched at substantially the same rate above both the fuse 1 and the contact pad 5, exposure to the etchant just long enough to create a window 9 exposing the contact pad 5 will also create a window 7 of the same depth above fuse element 1. Since the fuse element 1 is positioned slightly lower than the contact pad, a thin layer of insulative material 13 will remain between the contact pad and the window thereabove, as desired. Unfortunately, this conventional procedure requires two separate photolithographic transfer processes: one for producing the primary circuit paths, including the contact pads; and another for producing the fuse elements. Separate chip layers and conductor materials are also required. This results in increased fabrication time, effort and expense.
Accordingly, it would be desirable to avoid the requirement of two photolithographic processes, layers and conductor materials in the production of a fused integrated circuit, as described above.